Programmable NAND memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S200000, C365S201000

Reexamination Certificate

active

07733697

ABSTRACT:
An electrically programmable memory including: an array of a plurality of memory cells arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks and each memory block including a plurality of memory pages; means for receiving an address corresponding to a respective memory block; selecting means for selecting the addressed memory block; and means for detecting a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers, each register corresponding to a respective memory block and storing an indication of the failure of the respective memory block; and means for reading the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

REFERENCES:
patent: 5579265 (1996-11-01), Devin
patent: 5659509 (1997-08-01), Golla et al.
patent: 5774646 (1998-06-01), Pezzini et al.
patent: 6507518 (2003-01-01), Hosono et al.
patent: 2002/0048191 (2002-04-01), Ikehashi et al.
patent: 2003/0035322 (2003-02-01), Wong
patent: 0 537 973 (1993-04-01), None
patent: 0 637 034 (1995-02-01), None
European Search Report for EP 04 10 3354 dated Apr. 25, 2005.

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