Programmable memory timing method and apparatus for programmably

Details Programmable memory timing method and apparatus for programmably Programmable memory timing method and apparatus for programmably

1991-12-20

1995-02-28

Coleman, Eric

Boots, shoes, and leggings

3642702, 3642703, 3642384, 364DIG1, G06F 900

Patent

active

053945417

ABSTRACT:
The present invention operates within a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing system. This RAM, termed the MCRAM, is used to store the timing information for memory operations. In particular, the MCRAM stores for each of the memory operations, Read, Write, and Refresh, the relevant information for RAS, CAS, LD, and AD timing signals. The presently preferred embodiment of the invention contemplates a particular programming process wherein the MCRAM is initially loaded with generic timing information which is acceptable to all possible DRAM memory modules. Following this loading operation, the processor obtains the ID number of the DRAMs within a particular memory module. This ID number is used in a look-up table to obtain the vendor-specific optimal timing for DRAMs corresponding to this ID number. The processor then writes this optimal timing information into the MCRAM. Thereafter, all memory operations to this particular memory module utilize this optimal timing information.

REFERENCES:
patent: 4785428 (1988-11-01), Bajwa et al.
patent: 4970687 (1990-11-01), Usami
patent: 5202857 (1993-04-01), Yanai
patent: 5276856 (1994-01-01), Norsworthy
IBM Technical Disclosure Bulletin, vol. 31, No. 9, Feb. 1989, New York, U.S.A., pp. 351-354. Entitled: Programmable Memory Controller.
IBM Technical Disclosure Bulletin, vol. 33, No. 6A, Nov. 1990, New York, U.S.A., pp. 269-272. Titled: Optimum Timing Auto-Configurable Microcoded Memory Controller.

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