Programmable memory device having reduced power consumption upon

Details Programmable memory device having reduced power consumption upon Programmable memory device having reduced power consumption upon

1980-11-10

1983-06-07

Popek, Joseph A.

Static information storage and retrieval

Powering

Conservation of power

G11C 700

Patent

active

043874495

ABSTRACT:
A memory device is capable of operating in a power down mode in which peripheral memory circuitry is inactivated, the power down mode being assumed in response to an unselect signal at any one of a plurality of chip enable terminals. In response to a write potential at the output terminal of the memory, a detector circuit will leave the output circuit inactivated but will activate any peripheral circuitry necessary for the write operation.

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