Programmable memory addressing

Details Programmable memory addressing Programmable memory addressing

1990-11-13

1995-02-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiplexing

36523001, G11C 800

Patent

active

053922522

ABSTRACT:
A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.

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patent: 4809234 (1989-02-01), Kuwashiro
patent: 4881206 (1989-11-01), Kadono
patent: 4899272 (1990-02-01), Fung et al.
patent: 5005157 (1991-04-01), Catlin

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