Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Comparing counts
Patent
1991-07-12
1992-11-17
Sikes, William L.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Comparing counts
G03B 2312
Patent
active
051649691
ABSTRACT:
A system and method counts the maximum and minimum number of continuous cycles in which a RISC system event occurs. Additionally, a hold enable input offers the functionality of counting max/min events that are not continuous in time. These maximum and minimum counts are useful for benchmarking performance measurements and for performance debugging. The system and method provides a self-test mode for component testing, as well as maximum, minimum, and accumulator counting modes for use in a programmable performance analysis system. These counting modes allow various aspects of a target system to be categorized for performance analysis. The system has applicability in workstations and RISC systems having high frequency requirements typically greater than 50 Mhz. In one embodiment, a programmable system designed to be utilized in a workstation environment makes use of two identical full speed clock counters and a comparator which are controlled by a PAL that implements a state machine to provide the above four modes of operation.
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Alley Richard K.
Riccio, Jr. Anthony L.
Hewlett--Packard Company
Ouellette Scott A.
Sikes William L.
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