Programmable low-power high-frequency divider

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S210000, C327S218000

Reexamination Certificate

active

07075350

ABSTRACT:
A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

REFERENCES:
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patent: 5828249 (1998-10-01), Sessions
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patent: 6275083 (2001-08-01), Martinez et al.
patent: 6744289 (2004-06-01), Nguyen et al.
patent: 6801069 (2004-10-01), Livolsi et al.

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