Programmable logic unit for arithmetic, logic and equality funct

Details Programmable logic unit for arithmetic, logic and equality funct Programmable logic unit for arithmetic, logic and equality funct

1995-10-10

1998-09-22

Malzahn, David H.

Boots, shoes, and leggings

36471601, 326 37, G06F 750, G06F 704

Patent

active

058124373

ABSTRACT:
An arithmetic logic unit is disclosed herein which overcomes problems in the art discussed above. In accordance with the present invention, an ALU includes a plurality of individual programmable logic units which selectively implement arithmetic, logic, and equality comparison operations. One bit of each of two or more input signals is provided to respective ones of the logic units. One of a plurality of function signals, each of which being set equal to the truth table for a particular arithmetic, logic, or equality operation, is selectably provided to each of the logic units. Each of the logic units multiplexes the function signal provided thereto according to the particular bits of the input signals received therein to generate first and second output signals. These first and second output signals provided by each of the logic units are combined in an adder such that the resulting bit pattern represents the selected arithmetic, logic, or equality operation of the two or more input signals.

REFERENCES:
patent: 4541067 (1985-09-01), Whitaker
patent: 5079446 (1992-01-01), Holzle
patent: 5398198 (1995-03-01), Mahant-Shetti et al.
patent: 5436574 (1995-07-01), Veenstra
patent: 5463327 (1995-10-01), Hastie

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