Programmable logic resource with data transfer synchronization

Details Programmable logic resource with data transfer synchronization Programmable logic resource with data transfer synchronization

2006-02-21

2006-02-21

Bui, Bryan (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S125000, C713S501000, C713S502000

Reexamination Certificate

active

07003423

ABSTRACT:
A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are routed to a reset register that controls the reset of a dynamic phase alignment circuit and a data realigner. The dynamic phase alignment circuit includes a phase-locked loop circuit, a J counter, and a deserializer. When the output signal of the reset register transitions from logic 1 to logic 0, the J counter begins to count and sets an enable signal accordingly. The enable signal, which controls the output of synchronized parallel data from the deserializer, is therefore phase associated with the programmable logic resource core clock. The synchronized parallel data is input to a data realigner which outputs the data based on the programmable logic resource core clock for input to the programmable logic resource core circuitry.

REFERENCES:
patent: 6650140 (2003-11-01), Lee et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
patent: 2004/0236977 (2004-11-01), Kizer et al.
U.S. Appl. No. 10/059,014, filed Jan. 29, 2002, Lee et al.
U.S. Appl. No. 10/713,877, filed Nov. 13, 2003, Churchill et al.
Altera Corporation, “Using Source-Synchronous Signaling with DPA in Stratix GX Devices,” Application Note 236, Version 1.0, Nov. 2002, pp. 1-18.

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