Programmable logic level input buffer

Details Programmable logic level input buffer Programmable logic level input buffer

1989-06-30

1991-03-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307448, 307481, 307270, H03K 19092, H03K 19096, H03K 19017, H03K 1704

Patent

active

049995294

ABSTRACT:
An integrated circuit input buffer is adapted to operate at either of two input levels, typically either TTL or CMOS logic levels. This is accommplished by switching an additional transistor (e.g. 15) into a path between the output node (e.g. 12) and a power supply voltage (e.g. V.sub.DD), thereby changing the ratio of the pull-up to pull-down devices. The desired input level may be selected after the manufacture of the device, as by applying a voltage to a package terminal, or by programming a register during operation of the integrated circuit.

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