Programmable logic integrated circuit devices with low...

Details Programmable logic integrated circuit devices with low... Programmable logic integrated circuit devices with low...

2007-03-27

2007-03-27

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S082000, C326S083000

Reexamination Certificate

active

10350551

ABSTRACT:
A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4333058 (1982-06-01), Hoover
patent: 4797631 (1989-01-01), Hsu et al.
patent: 5067007 (1991-11-01), Kanji et al.
patent: 5491455 (1996-02-01), Kuo
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5703532 (1997-12-01), Shin et al.
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 5767699 (1998-06-01), Bosnyak et al.
patent: 5880599 (1999-03-01), Bruno
patent: 5896057 (1999-04-01), Chicca et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 5949253 (1999-09-01), Bridgewater, Jr.
patent: 5977796 (1999-11-01), Gabara
patent: 5977819 (1999-11-01), Sanwo et al.
patent: 5994921 (1999-11-01), Hedberg
patent: 6005438 (1999-12-01), Shing
patent: 6025742 (2000-02-01), Chan
patent: 6054874 (2000-04-01), Sculley et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6252419 (2001-06-01), Sung et al.
“LVDS Owner's Manual; Design Guide”, National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7.
ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01, Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
Optimized Reconfigurable Cell Array (ORCA), OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, Lucent Technolgies Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note”, Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31)”, Xilinx Corporation, pp. 1-14.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0)”, Xilinx Corporation, pp. 1-24.
DY6000 Family, FAST Field Programmable Gate Array, DY6000 Family Datasheet, Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.
“Block Diagram for NSM LVDS Output Buffer”, “Circuit Trace from National Semiconductor Device”, National Semiconductor Corporation, Oct. 1998.

Affiliated with

Also associated with

Rating

Programmable logic integrated circuit devices with low... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic integrated circuit devices with low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic integrated circuit devices with low... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3726594