Programmable logic gates and networks

Details Programmable logic gates and networks Programmable logic gates and networks

1983-03-30

1985-01-22

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307451, 364716, H03K 19094, H03K 19177

Patent

active

044954271

ABSTRACT:
The network connections of the channels of complementary symmetry MOS FET's in a logic gate or array are altered electrically to program different logic responses to logic inputs. To this end, certain of the FET's are gate-injection or substrate-injection MOS FET's.

REFERENCES:
patent: 3760380 (1973-09-01), Hoffman et al.
patent: 3818452 (1974-06-01), Greer
patent: 4041459 (1977-08-01), Horninger
patent: 4091293 (1978-05-01), Ando
patent: 4091359 (1978-05-01), Rossler
patent: 4122544 (1978-10-01), McElroy
patent: 4130890 (1978-12-01), Adam
patent: 4162504 (1979-07-01), Hsu
patent: 4175290 (1979-11-01), Harari
patent: 4209849 (1980-06-01), Schrenk
patent: 4237547 (1980-12-01), Smith
patent: 4258378 (1981-03-01), Wall
patent: 4313106 (1982-01-01), Hsu
patent: 4375087 (1983-02-01), Wanlass
Chao, "Electrically Alterable Read-Only Memory Array", IBM Tech. Disc. Bull., vol. 25, No. 1, Jun. 1982, pp. 41-43.
Krick, "Complementary MNOS Electronically Alterable Read-Only Memory", IBM Tech. Disc. Bull., vol. 13, No. 1, Jun. 1970, pp. 263-264.
Scheibe et al., "Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS", IEEE Trans. Elect. Devices, vol. ED-24, No. 5, May, 1977, pp. 600-606.
Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", IEEE-JSSC, vol. SC-10, No. 5, 10/75, pp. 331-336.
Wilder et al., "Multiple Selective Write Alterable Read-Only Storage", IBM TDB, 2/75, vol. 17, No. 5, pp. 2595-5.
RCA Tech Note 1152, L. B. Medwin & A. C. Ipri "Floating Transistor-Gate Field Effect Transistor Memory Device" mailed May 24, 1976.
RCA Tech Note No. 1185, L. B. Medwin & A. C. Ipri, "FACMOS EAROM" mailed Jun. 24, 1977.
Array Logic Using FAMOS Devices, S. Dasgupta, IBM Technical Disclosure Bulletin, vol. 17, No. 10, pp. 2897-2899, Mar. 1975.
Electrically Programmable Logic Array, Grice et al., IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980.

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