Programmable logic device with two dimensional memory addressing

Details Programmable logic device with two dimensional memory addressing Programmable logic device with two dimensional memory addressing

1996-12-02

1998-12-01

Fears, Terrell W.

Electricity: electrical systems and devices

Electric charge generating or conducting means

36523003, G11C 1300

Patent

active

058448543

ABSTRACT:
A programmable logic array integrated circuit device having a memory array in which data can be accessed in either a transposed or nontransposed mode. The memory array has multiple rows and columns of memory cells. Each row of cells can be viewed as a matrix made up of virtual rows and virtual columns. Data in a given row of the memory array can be accessed using nontransposed data words that contain data bits corresponding to cells in the virtual rows. Data in the given row can also be accessed using transposed data words that contain data bits corresponding to cells in the virtual columns.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4593373 (1986-06-01), Kiuchi
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4677318 (1987-06-01), Veenstra
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4751671 (1988-06-01), Babetski et al.
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4774421 (1988-09-01), Hartmann
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4942541 (1990-07-01), Hoel et al.
patent: 5027326 (1991-06-01), Jones
patent: 5121006 (1992-06-01), Pedersen
patent: 5128559 (1992-07-01), Steel
patent: 5146428 (1992-09-01), Tanimura
patent: 5220214 (1993-06-01), Pedersen
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5274596 (1993-12-01), Watanabe
patent: 5350954 (1994-09-01), Patel
patent: 5371422 (1994-12-01), Patel et al.
patent: 5396608 (1995-03-01), Garde
patent: 5506850 (1996-04-01), Osann, Jr.
patent: 5541530 (1996-07-01), Cliff et al.
patent: 5543732 (1996-08-01), McClintock et al.
patent: 5592106 (1997-01-01), Leong et al.
patent: 5614840 (1997-03-01), McClintock et al.
John L. Nichols, "A Logical Next Step for Read-Only Memories", Electronics, Jun. 12, 1967, pp. 111-113.
Floyd Kvamme, "Standard Read-Only Memories Simplify Complex Logic Design", Electronics, Jan. 5, 1970, pp. 88-95. Easily", Electronics, May 11, 1970, pp. 104-11.
William I. Fletcher et al., "Simplify Sequential Circuit Designs", Electronic Design, Jul. 8, 1971, pp. 70-72.
Howard A. Scholl et al., "Design of Asynchronous Sequential Networks Using Read-Only Memories", IEEE Transactions on Computers, vol. C-24, No. 2, Feb. 1975, pp. 195-206.
Arnold Weinberger, "High-Speed Programmable Logic Array Adders", IBM J. Res. Develop., vol. 23, No. 2, Mar. 1979, pp. 163-178.
Yahiko Kambayashi, "Logic Design of Programmable Logic Arrays", IEEE Transactions on Computers, vol. C-28, No. 9, Sep. 1979, pp. 609-617.
R.C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967.
S.E. Wahlstrom, "Programmable Logic Arrays--Cheaper by the Millions," Electronics, Dec. 11, 1967, pp. 90-95.
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, Chapters VI and IX, pp. 229-254 and 369-422.
El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 394-398.
El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, vol. 24, No. 3, Jun. 1989, pp. 752-762.
"XC5000 Logic Cell Array Family, Technical Data, Advance Information," Xilinx, Inc., Feb. 1995.

Affiliated with

Also associated with

Rating

Programmable logic device with two dimensional memory addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device with two dimensional memory addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device with two dimensional memory addressing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2400906