Programmable logic device with power-saving architecture

Details Programmable logic device with power-saving architecture Programmable logic device with power-saving architecture

2008-05-20

2008-05-20

Dinh, Son (Department: 2824)

Static information storage and retrieval

Powering

C365S227000, C365S229000

Reexamination Certificate

active

11235616

ABSTRACT:
A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

REFERENCES:
patent: 6828823 (2004-12-01), Tsui et al.
patent: 7184354 (2007-02-01), Song
patent: 2002/0135398 (2002-09-01), Choi et al.
patent: 2005/0035782 (2005-02-01), Swami
Lattice Semiconductor Corporation, ispMACH™ 4000V/B/C/Z Family, 3.3V/2.5V/1.8V In-System Programmable SuperFAST™High Density PLDs Data Sheet, Dec. 2004, pp. 1-13.
XILINX®, Spartan-3L Low Power FPGA Family, Preliminary Product Specification, Sep. 15, 2002, pp. 1-10.

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