Programmable logic device with observability and preload circuit

Details Programmable logic device with observability and preload circuit Programmable logic device with observability and preload circuit

1988-07-12

1990-07-03

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307454, 307466, H03K 1760

Patent

active

049393910

ABSTRACT:
A programmable array logic device including a programmable logic array, at least one register pair, a multiplexer coupled to the register pair so that they can share a common I/O pin, and an observability buffer for controlling the multiplexer. A dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode. When in the logic mode, either the output of a buried state register or a output register is observed at the I/O pin under the control of a product term generated by the logic array. When in the preload mode the register to be preloaded is selected by an externally provided preload select signal. In the verification mode, which typically follows a programming mode, individually selected product terms within the logic array can be observed by clocking them into the register pairs.

REFERENCES:
patent: 3522444 (1970-08-01), Lourie
patent: 3962589 (1976-06-01), Priel et al.
patent: 4400635 (1983-08-01), Mazgy
patent: 4471239 (1984-09-01), Ohba
patent: 4689502 (1987-08-01), Shimauchi et al.
patent: 4703202 (1987-10-01), Enomoto et al.

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