Programmable logic device with logic signal delay compensated cl

Details Programmable logic device with logic signal delay compensated cl Programmable logic device with logic signal delay compensated cl

1998-05-26

2000-10-03

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, G06F 110

Patent

active

061278653

ABSTRACT:
An integrated circuit programmable logic device comprising: a plurality of programmable logic elements that are responsive to clock signals; a clock signal generation circuit which produces a first clock signal; a first phase shifting element which produces a second clock signal which is a phase-shifted version of the first clock signal, shifted in phase by an amount which compensates for a logic signal delay; and a clock signal distribution network which distributes the first and second clock signals among the programmable logic elements.

REFERENCES:
patent: 4839604 (1989-06-01), Tanahashi
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5550783 (1996-08-01), Stephens, Jr. et al.
patent: 5578945 (1996-11-01), Flora
patent: 5668504 (1997-09-01), Ramalho
Altera Corporation, 1996 Data Book, A-DB-0696-01, Jun. 1996.
Chen, Dao-Long, "Designing On-Chip Clock Generators," 1992 IEEE Circuits and Devices, pp. 32-36 (Jul. 1992).
Gardner, F., "Phase Accuracy of Charge Pump PLL's," IEEE Transactions on Communications, vol. Com-30, No. 10, pp. 2362-2363 (Oct. 1982).
Steinke, G., "Using PLL Technology In A Programmable Logic Device," Electronic Design, pp. 123-134, (Jul. 7, 1997).

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