Programmable logic device placement method utilizing weighting f

Details Programmable logic device placement method utilizing weighting f Programmable logic device placement method utilizing weighting f

1996-11-13

1998-08-04

Donaghue, Larry D.

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395376, 395562, 395564, 39580032, 39580033, 39580037, 39580039, 39580042, 39580043, 364718, 364735, 3647505, G06F 300

Patent

active

057908826

ABSTRACT:
A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.

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Xilinx Programmable Gate Array Data Book, pp. 3-1 through 3-67, 1996, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
C. M. Fiduccia, R. M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions", Paper 13.1, pp. 175-181, 19th Design Automation Conference, 1982.
Zafar Hasan, David Harrison, Maciei Ciesielski, "A Fast Partitioning Method for PLA-Based FPGAs", pp. 34-39, IEEE Design & Test of Computers, 1992.

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