Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1994-04-01
1995-07-04
Fears, Terrell W.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
365 78, 36518904, 36518912, G11C 1300
Patent
active
054306876
ABSTRACT:
A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.
REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4706216 (1987-11-01), Carter
patent: 4750155 (1988-06-01), Hsieh
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 4870302 (1989-09-01), Freeman
patent: 5148390 (1992-09-01), Hsieh
patent: 5198705 (1993-03-01), Galbraith et al.
patent: 5243238 (1993-09-01), Kean
patent: 5258668 (1993-11-01), Cliff
patent: 5260611 (1993-11-01), Cliff
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5267187 (1993-11-01), Hsieh
patent: 5280202 (1994-01-01), Chan
Erickson Charles R.
Hung Lawrence C.
Fears Terrell W.
Sueoka Greg T.
Xilinx , Inc.
Young Edel M.
LandOfFree
Programmable logic device including a parallel input device for does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic device including a parallel input device for , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device including a parallel input device for will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-765783