Coded data generation or conversion – Digital code to digital code converters – Programmable structure
Reexamination Certificate
2000-10-06
2002-08-20
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Programmable structure
C326S041000, C375S324000
Reexamination Certificate
active
06437713
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method and apparatus for communication with a programmable logic device using both amplitude and phase modulation.
BACKGROUND INFORMATION
A field programmable gate array (FPGA) available from Xilinx Inc. of San Jose, Calif., includes multiple delay-locked loops (DLLs). One such DLL is., for example, usable to provide low clock skew between a clock signal output from the FPGA and a clock signal internal to the FPGA. The FPGA is, however, configurable so that a user can use the DLL for other purposes. For additional information on a Xilinx FPGA and its DLLs, see: 1) U.S. patent application Ser. No. 09/482,741 entitled “Deskewing Clock Signals For Off-Chip Devices”, by Bapat et al., filed Jan. 13, 2000; and 2) XAPP 132, “Using the Virtex Delay-Locked Loop”, v.2.2, pages 1-15 (May 23, 2000), both of which documents are incorporated herein by reference.
An FPGA of the type described above generally interacts with external circuitry by sending signals to the external circuitry from input/output (I/O) terminals of the FPGA and/or by receiving signals from external circuitry via I/O terminals of the FPGA. The term “FPGA” as it is used here denotes an FPGA integrated circuit housed in an integrated circuit package. Accordingly, each signal passing onto or from the FPGA integrated circuit passes through an I/O terminal of the package. Over time, there has been an increase in the size and complexity of FPGA integrated circuits, but there has not been a commensurate increase in the number of I/O terminals available on standard packages. Consequently, the functionality of user-specific designs realized using such FPGAs is sometimes “I/O constrained”. The FPGA integrated circuit can be designed to have the desired I/O resources, but the packages available for containing the FPGA integrated circuit have a restrictively small number of I/O terminals available. Not only are today's user-specific designs often “I/O constrained” in this way, but the divergence between the I/O capability of the FPGA integrated circuit and the I/O capability of the package is likely to widen in the future. A solution is desired.
SUMMARY
A programmable logic device (for example, a field programmable gate array) makes better use of its I/O terminals (for example, its package pins) by both amplitude and phase encoding information into a single DATA signal. This single DATA signal can be transmitted from or received onto the FPGA via just one I/O terminal, as opposed to many I/O terminals. In one specific example, information is encoded into four different voltage levels and four different phases. An amplitude/phase encoder is described that includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop. The slaved delay lines are used to phase encode the information into the DATA signal. An amplitude/phase decoder is also described that includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop. The slaved delay lines are used to decode the phase information from the DATA signal. A coding scheme is employed to ensure that an amplitude change occurs in the data such that the decoder can properly detect encoded phase information.
Other embodiments are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.
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JeanGlaude Jean Bruner
Jeanpierre Peguy
Wallace T. Lester
Xilinx , Inc.
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