Programmable logic device

Details Programmable logic device Programmable logic device

1991-09-11

1993-04-13

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, 364716, H03K 19094, H03K 14177

Patent

active

052025926

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a programmable logic device with which user is capable of realizing any combinational logic circuit at his hand, and more specifically to a programmable logic device where a layout area thereof can be reduced and where a working speed can be improved.
2. Background Art
There are known in prior practice programmable logic devices (hereinafter referred to as PLD) with which a user can realize an arbitrary logic circuit at his hand. The PLD includes a plurality of programmable logic elements (hereinafter referred to as PLE) disposed on a chip, each of which elements has its input and output optionally connectable through programmable wiring. Use of such a PLD assures a desired large-scale circuit by allowing a user to select functions of the PLEs and wirings thereamong PLEs.
Those prior art PLEs include PLAs (programmable logic array) each having programmable AND planes and OR planes, further including logic circuits of a table look-up type using a memory.
The present applicant has proposed previously a programmable logic device as described in Japanese Patent Application No. 63-6197, wherein as illustrated in FIG. 8 there are provided a required number (8 in the figure) of coincidence detector circuits 20A through 20H of a combination of N input signals (four input signals I.sub.0 through I.sub.3 in the figure) whereby there are eliminated such wasteful programmable elements as in the table look-up system, and wherein product term lines of the PLA are expanded by a first expansion circuit 31 and likewise outputs (coincidence signals) of coincidence detector circuits of other PLEs are connected therewith whereby coincidence signals can be outputted correspondingly to input signals of the number greater than that of the input signals, and further wherein coincidence signals of further other PLEs are connected by a second expansion circuit 32 to expand the number of combinations of stored input signals exceeding the number of the coincidence detector circuits whereby the number of input signals into the coincidence detector circuit of each PLE can be set to be smaller.
The present applicant has further proposed as the foregoing coincidence detector circuit 19, which comprises, as illustrated in FIG. 9, invertors 22.sub.0 through 22.sub.3 each for inverting input signals I.sub.0 through I.sub.3, negative logic switching elements 23.sub.0 through 23.sub.3 each for conducting or interrupting outputs from the invertors 22.sub.0 through 22.sub.3, positive logic switching elements 24.sub.0 through 24.sub.3 each for allowing the input signals I.sub.0 through I.sub.3 to be conducted therethrough or interrupted thereby intactly; first memory cells M.sub.00 through M.sub.30 each for complementarily controlling on/off states of the positive and negative logic switching elements 24.sub.0 through 24.sub.3 and 23.sub.0 through 23.sub.3 ; a plurality (four in the figure) of selectors 21.sub.0 through 21.sub.3 each including two-input NAND gates 25.sub.0 through 25.sub.3 each for issuing the negation of a logical product of connection points of outputs from said positive logic switching elements 24.sub.0 through 24.sub.3 and those from said negative logic switching elements 23.sub.0 through 23.sub.3, and outputs of second memory cells M.sub.01 through M.sub.31 for setting a don't care input which may take any logical stage, and each further including said second memory cells M.sub.01 through M.sub.31, and a four-input AND gate 26 for issuing as the coincidence output a logical product of outputs from the selectors 21.sub.0 through 21.sub.3.
Each of the memory cells M.sub.00 through M.sub.30 and M.sub.01 through M.sub.31 comprises a pair of SRAMs (static random access memory) 27A, 27B connected parallely oppositely to each other as illustrated in FIG. 10 for example, one output terminal of which issues an output Q and the other of which issues an inverted output Q.
In the coincidence detector circuit 19, any one of the negative and positive logics of the input sig

REFERENCES:
patent: 4796229 (1989-01-01), Greer, Jr. et al.
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4930098 (1990-05-01), Allen
patent: 4935737 (1990-06-01), Izbicki et al.

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