Programmable logic circuit with delayed input and feeback

Details Programmable logic circuit with delayed input and feeback Programmable logic circuit with delayed input and feeback

1992-03-04

1992-10-06

Smith, Jerry

Boots, shoes, and leggings

G06F 926

Patent

active

051538229

ABSTRACT:
A programmable logic circuit includes a memory sector and other logic elements which are laid peripherally, wherein the memory sector is prestored with possible input data and output data which are derived by fuzzy reasoning. In application, observed data on an objective entity outside is first treated by a logic element to convert the data to digital form and then input as an address in the memory sector wherein the input observed data is converted by fuzzy logic to an operative data, which is sent to downstream to subsequent circuit elements to control a device. The illustrated embodiment is for an air-conditioning system wherein introduction of a memory sector having fuzzy logic based data will prevent erroneous actions in the downstrem devices which are caused by erroneously input data, in the process of processing data by a conventional programmable logic circuit.

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patent: 4628435 (1986-12-01), Toshiro et al.
patent: 4700326 (1987-10-01), Florine
patent: 4744022 (1988-05-01), Kumar et al.
patent: 4963768 (1990-10-01), Agrawal et al.
H. R. van Nauta Lemke and Wang De-Zhao, "Fuzzy PID Supervisor", 1985 from 24th IEEE Conference on Decision and Control, vol. 1, pp. 602-608.

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