Programmable logic circuit having bidirectional data lines

Details Programmable logic circuit having bidirectional data lines Programmable logic circuit having bidirectional data lines

1989-09-06

1991-01-15

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307443, 34082583, H03K 19177

Patent

active

049856502

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to a programmable arrangement for operating binary input signals upon employment of a matrix that is composed of data lines, of coupling lines crossing therewith and of coupling elements arranged at the coupling points of the data lines and coupling lines.
Programmable circuits, abbreviated as PLA, are known (see, for example, Weiss, Horninger, Integrierte MOS-Schaltungen, Springer-Verlag 1982, pages 295 through 298). Such programmable circuits contain an AND level and an OR level. The operation of the input signals according to a function table stored in the AND level ensues in the AND level. These operation results of the AND level that are also referred to as product terms are supplied to the OR level and are operated there according to the function table contained in the OR level to form what are referred to as sum terms. The sum terms are output at the outputs of the OR level. Such a PLA has input lines that lead to the AND level and output lines that lead out from the OR level available to it.


SUMMARY OF THE INVENTION

The object underlying the invention is comprised in constructing a programmable circuit arrangement such that it can be bidirectionally operated; i.e., the lines (data lines) entering into the programmable circuit arrangement can be input lines or output lines.
In a programmable circuit arrangement of the species initially cited, this object is achieved by the characterizing features of patent claim 1.
The programmable circuit arrangement is thus no longer composed of a separately executed AND level and OR level. On the contrary, it is composed of a matrix of crossing data lines and coupling lines and of switching elements arranged according to a function table at the coupling points between the data lines and the coupling lines. Dependent on a control signal, the data lines can be operated as input line or as output line. The coupling lines are terminated such that the input signals coupled from the data lines operated as input lines onto the coupling lines are subject to an AND operation. The data lines are terminated such that, given operation as output line, the signals coupled in from the coupling lines are subjected to a 0R operation.
The switching elements are executed such that a function table having a trivalent logic can be stored. Further, there are four possibilities of how the output value of a data line operated as output line can be determined. The user can select one of the four possibilities. The plurality of logic functions can be realized in such a universally constructed programmable circuit without additional function lines.
Improvements of the invention derive from the subclaims.


BRIEF DESCRIPTION OF THE DRAWINGS

The invention shall be set forth in greater detail with reference to exemplary embodiments that are shown in the figures. Shown are:
FIG. 1 a block circuit diagram of the programmable circuit arrangement;
FIG. 2 a wiring diagram of the programmable circuit arrangement;
FIG. 3 the programming of the switching elements;
FIG. 4 a portion of the circuit arrangement wherein a data line is operated as input;
FIG. 5 a portion of the circuit arrangement wherein a data line is operated as output;
FIG. 6 an auxiliary circuit with which the coupling lines can be disconnected;
FIG. 7 a programmed circuit arrangement.


DESCRIPTION OF THE PREFERRED EMBODIMENT

A logic function can be expressed by the disjunctive normal form; for example, the output variables derive in the form YO=X1 X2+Xl X2, Yl=XlX2 X is thereby the inverted X.
The function table for this function reads:


______________________________________ X1 X2 Y0 Y1 ______________________________________ 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 ______________________________________
The function can be realized in that the required AND operation is produced and the OR operation is formed therefrom. This can be achieved with the assistance of a programmable circuit arrangement in that the required connections between the input variables or, respec

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Varadarajan, "Universal Logic Array", IBM TDB, vol. 20, No. 1, Jun. 1977, pp. 189-190.
Weiss, Horninger, "Integrierte MOS-Schaltungen", Springer Verlag, pp. 295-298.
Electronique et Microelectronique Industrielles, Nr. 215, Feb. 15, 1976, (Paris Fr), H. Lilen: "Qu'est-ce qu'un reseau logique programmable (PLA)?", pp. 19-24 see FIGS. 3, 4.

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