Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-11-02
1992-09-01
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307 465, H03K 19177
Patent
active
051441667
ABSTRACT:
A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
REFERENCES:
patent: Re31287 (1985-06-01), Patil
patent: 3400379 (1968-09-01), Harman
patent: 3446990 (1969-05-01), Goldberg
patent: 3731073 (1973-05-01), Moylan
patent: 3818252 (1974-06-01), Chiba et al.
patent: 3818452 (1974-06-01), Greer
patent: 3912914 (1975-10-01), Moylan
patent: 4034356 (1975-12-01), Howley et al.
patent: 4068214 (1978-07-01), Patil
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4240094 (1980-12-01), Mader
patent: 4293783 (1981-10-01), Patil
patent: 4331950 (1982-05-01), Barabas
patent: 4336601 (1979-07-01), Tanaka
patent: 4414547 (1981-10-01), Knapp et al.
patent: 4422072 (1983-12-01), Caulan
patent: 4431928 (1984-02-01), Skokan
patent: 4451895 (1984-05-01), Sliwkowski
patent: 4467439 (1984-08-01), Rhodes
patent: 4600846 (1986-07-01), Burrows
patent: 4611236 (1986-09-01), Sato
patent: 4642487 (1987-02-01), Carter
patent: 4700187 (1987-10-01), Furtek
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4992680 (1991-02-01), Beuedetti et al.
patent: 5001368 (1991-03-01), Cliff
patent: 5003200 (1991-03-01), Sakamoto
patent: 5019736 (1991-05-01), Furtek
Patil and Welch, "A Programmable Logic Approach for VLSI", IEEE Transactions of Computers, vol. C-28, No. 9, pp. 594-601, (Sep. 1979).
Xilinx and Hamilton/Avnet, Present Logic Cell Arrays.TM.: "The User Programmable Gate Arrays", Xilinx, Inc.
Synder, "Introduction to the Configurable, Highly Parallel Computer", IEEE Computer, pp. 47-55, (Jan. 1982).
Patil, "A Micro-Modular Implementation of the Control Modular of Basic Macro-Modular Circuits", M.I.T. Computer Str. Group Memo 43, (Oct. 1969).
Stucki, "Synthesis of Level Sequential Circuits", Computer Systems Labs., Washington University, (date not available).
Patil and Dennis, "Speed Independent Asynchronous Circuits", M.I.T. Computer Str. Group Memo No. 54, (Jan. 1971).
Patil and Dennis, "The Description and Realization of Digital Systems", M.I.T. Computer Str. Group Memo No. 71, (Oct. 1972).
Patil, "Circuit Implementation of Petri Nets", M.I.T. Computer Str. Group Memo No. 73, (Dec. 1972).
Jump, "Asynchronous Control Arrays", IEEE Trans. on Computers, vol. C-23, No. 10, (Oct. 1974).
Patil, "Cellular Arrays for Asynchronous Control", M.I.T. Computer Str. Group Memo No. 122, (Apr. 1975).
Misunas, "Petri Nets and Speed Independent Designs", Comm. of the ACM, vol. 16, No. 8, pp. 474-481, (Aug. 1973).
Agerwala, "Putting Petri Nets to Work", IEEE Computer, pp. 85-94, (Dec. 1979).
Seitz, "Concurrent VLSI Architectures", IEEE Trans. on Computers, vol. C-33, No. 12, pp. 1247-1265, (Dec. 1984).
Snyder, "Parallel Programming and the Poker Programming Environment", IEEE Computer, pp. 27-33, (Jul. 1984).
"Storage/Logic Arrays Finally Get Practical", Electronics, pp. 29-33, (Jan. 1986).
Israelson et al., "Comparison of the Path Programmable Logic Design Methodology . . . ", IEEE Int'l. Conference on Computer Design, pp. 73-76, (Oct. 1985).
Barney, "Logic Designers Toss Out the Clock", Electronics, pp. 42-45, (Dec. 1985).
Collett, "Programmable Logic Soars Into New Dimensions", Digital Design, pp. 42-54, (Apr. 1985).
Willis, "Ultra-Fine Grain Processing Architectures", M.I.T. VLSI Memo No. 85-245, (May 1985).
Pacas-Skewes, "A Design Methodology for Digital Systems Using Petri Nets", Ph.D. dess, U. of Texas at Austin, (1979).
Kukreja et al., "Combinational and Sequential Cellular Structures", IEEE Transactions on Computers, vol. C-22, No. 9, pp. 813-823, (Sep. 1983).
Manning, "An Approach to Highly Integrated, Computer-Maintained Cellular Arrays", IEEE Transactions on Computers, vol. C-26, No. 6, pp. 536-552, (Jun. 1977).
King, "Subcircuits on Linear Arrays--A New Array Topology", IEEE Proceedings of the IEEE 1985 Custom Integrated Circuits Conferences, pp. 470-474, (May 1985).
Hartmann, "CMOS Erasable Programmable Logic Devices TTL Replacement Made Easy", Electro and Mini-Micro Northeast Conference Record, pp. 1-9, (Apr. 1985).
Karatsu et al., "An Integrated Design Automation System for VLSI Circuits", IEEE Design & Test of Computers, vol. 2, No. 5, pp. 17-26, (Oct. 1985).
Krug et al., "Abaenderbare Gatter-Anordningen", Elektronik, vol. 35, No. 22, pp. 170-171, 174-176, (Oct. 1986).
Browder Edward H.
Camarota Rafael C.
Furtek Frederick C.
Ho Walford W.
Concurrent Logic, Inc.
Hudspeth David
LandOfFree
Programmable logic cell and array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic cell and array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic cell and array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-769644