Programmable logic arrays with each array column divided into a

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307469, H03K 1704

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active

049029185

ABSTRACT:
Programmable logic arrays (PLAs) in the form of a matrix having each array column consisting of a plurality of FETs (Field Effect Transistors) in which cell arrays constituting each array column for producing logical product output signals are divided into a plurality of array blocks so as to reduce the number of the FETs to be connected in series in each array block and to eventually reduce the series resistance of each of the array columns, and the output signals from each of the array blocks thus divided are applied to the input terminals of each logical circuit so as to reduce each combined logical product from each logical gate, thereby realizing high speed operation for the PLAs.

REFERENCES:
patent: 3953743 (1976-04-01), Hollingsworth
patent: 4415819 (1983-11-01), Mathes
patent: 4430583 (1984-02-01), Shoji
patent: 4644192 (1987-02-01), Fisher
patent: 4659948 (1987-04-01), Sunter et al.
patent: 4758746 (1988-07-01), Birkner et al.
Cases et al, "Improving the Performance of a Transfer Gate PLA Structure", IBM T.D.B., vol. 25, No. 4, Sep. 1982, pp. 2215-2216.

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