Programmable logic arrays

Details Programmable logic arrays Programmable logic arrays

2001-02-12

2002-05-28

Tolar, Michael (Department: 2819)

Electrical transmission or interconnection systems

Plural supply circuits or sources

One source floats across or compensates for other source

C326S041000, C326S112000

Reexamination Certificate

active

06396168

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits such as reprogrammable memories, and, more particularly, to a programmable logic array including at least one AND plane or at least one OR plane.
BACKGROUND OF THE INVENTION
The design of logic circuitry may sometimes require the use of complex combinatorial circuitry that depends upon a clock signal. For example, this may be the case in a state machine that implements a sequential algorithm and has its combinatorial circuitry separated from its sequential storage circuitry. A basic scheme of a state machine may be seen in FIG.
1
.
Current design approaches formulate the description of the state machine in a high level language (e.g., VHDL) to devise the algorithm. Once the methods are described in a language that may be synthesized (i.e., a high level language that can be interpreted by software to automatically synthesize the described logic network), the combinatorial circuitry can be implemented either with elementary logic gates or with a programmable logic array (PLA). These two solutions have their own advantages and disadvantages, the details of which are beyond the scope of the ensuing description.
What should be emphasized is that the implementation of logic gates is generally required and, as a result, the algorithm may not be modified in a simple manner. In fact, if a logic gate is to be implemented with complementary metal oxide semiconductor (CMOS) technology, the masks used for defining transistors will require modification, particularly the mask defining the active areas used during the first process step. On the other hand, by using a PLA the algorithm may be completely and simply changed by using a very limited number of masks and, therefore, process steps.
In other cases, such as that of FLASH erasable programmable read-only memories (EPROMs), reprogrammability is very important because the algorithm may sometimes require changes or updating during the life span of the device. This may occur during a debug phase or may follow from specific requirements which were not anticipated at the time of designing the device. Due to their relevance in the present context, the ensuing description will make reference to FLASH EPROM memories, although the invention may also be applied to other reprogrammable memories.
In order to clarify the technical problem overcome by the invention, reference is now made to FIG.
2
. The nodes of the graph represent the states of the machine. Three bits individuate these states, whereas the branches labeled with the letters represent the state transitions.
A truth table of the machine of
FIG. 2
is shown in FIG.
3
. The states of the machine are coded by the variable STATE(
0
), STATE(
1
) and STATE(
2
) which represent the least significant bit, the intermediate bit and the most significant bit, respectively, of the group of three bits that individuate a certain current state. Variables FUTURE(
0
), FUTURE(
1
) and FUTURE(
2
) represent the least significant bit, the intermediate bit and the most significant bit, respectively, of the group of three bits that individuate a future state reached as a result of a certain transition. Variables OUT(n) and IN(n) represent the bits of the logic input and output logic signals of the machine corresponding to a certain transition. Dashes represent “don't care” symbols.
A hardware embodiment including a PLA implementing the truth table of
FIG. 3
is shown in
FIGS. 5 and 6
. The PLA is built according to an AND-OR pre-charge and evaluation scheme. The combinatory circuitry COMBINATORIAL LOGIC that implements the PLA has 7 inputs, 9 minterms and 8 outputs.
As may be seen in
FIG. 5
, the AND plane of the PLA includes an array of transistors ordered in rows and columns. The transistors of a same column are connected in series through their respective current terminals, whereas the control terminals of the transistors belonging to the same row are connected in parallel. The top row of the array drives the start-up of the processing, whereas the bottom row extracts the computed values once the processing is completed.
The OR plane of the PLA, shown in
FIG. 6
, is instead formed by an array of transistors organized in row and columns which carry out the logic sum of the input minterms and by an output buffer. The transistors that belong to the same column of the array have their control terminals connected to a respective control line coupled to a certain minterm and a first current terminal connected to a reference potential. Also, the transistors of a same row have their second current terminal either connected or not to a respective output line. The output buffer (which appears on the left hand side of the figure) includes a column of inverters, each of which is connected to a respective output line and to a respective enabling transistor connected between the respective output line and the supply voltage VDD.
The PLA is a pre-charge and evaluation circuit. That is, the internal nodes are first pre-charged and then discharged during the evaluation phase if the input pattern corresponds to the expected one. To ensure that the outputs are read at the instant they assume a valid value (i.e., only when all the transistors function in a steady state), the PLA is provided with a dummy path DUMMY, as seen in
FIGS. 5 and 6
, that is designed to be the slowest of all paths. This dummy path DUMMY includes a set of as many transistors as the number of independent logic variables needed to implement the machine.
Because the dummy path has the largest number of transistors among the various paths of the PLA, it will consequently also be the slowest to reach a steady state of operation. Therefore, when a signal propagates through all the dummy path's transistors, all of the other input signals will have propagated through their respective paths and the evaluation phase may thereby be completed.
A possible timing diagram of the signals represented in the table of
FIG. 3
relative to the “E” transition is shown in FIG.
4
. The pre-charge phases of the AND (CPPA) and OR (CPPO) plane are active low and are out-phased among them. This is so that the output of the AND plane of the PLA may reach a steady state before the start of the processing carried out by the OR plane of the PLA. Before the CPPA signal enables the AND plane, the variables STATE(n) and IN(n) assume their respective values. Once the charge phase is completed with the disabling of the CPPO signal, the outputs OUT(n) and FUTURE(n) assume their respective final values. These are read only when the DUMMY path reaches a steady state and has delivered an OUTDUMMY output signal.
As shown in
FIGS. 5 and 6
, a combinatorial network having an “i” number of input variables may be realized with a PLA with 2*I inputs, i.e., the “i” input variables plus their respective inverted logic signal. This occurs because in order to ensure the programmability of the PLA the input variables and the respective inverted logic signals should be available. Let us consider a AND-OR PLA with 2*I inputs, “p” minterms and “o” outputs, for example. To implement the AND plane on silicon there must be enough space for 2*i*p transistors for the content, 2*i transistors for the DUMMY PATH, 2*(p+1) transistors for the pre-charge of the minterms, and p inverters. In order to implement an OR plane there must be enough silicon area for o*p transistors for the content, o+p+1 transistors for the DUMMY PATH, o+1 transistors for the pre-charge of the minterms, and o+1 inverters.
Referring to
FIG. 5
, different space intervals between the transistors of a same column are shown for convenience, i.e., transistors are shown at some locations while at other locations only short-circuits are shown. In reality, the transistors of the PLA are uniformly distributed on the silicon surface. However, only those transistors that do not form a minterm are short-circuited and they are depicted in the figure as simple short-circuits, whereas the transistors corresponding to the

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