Programmable logic array with test capability in the unprogramme

Details Programmable logic array with test capability in the unprogramme Programmable logic array with test capability in the unprogramme

1982-12-03

1985-06-25

Weldon, Ulysses

Communications: electrical

Continuously variable indicating

With meter reading

34082585, 29574, 307465, 365 96, H04Q 0000

Patent

active

045257140

ABSTRACT:
A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted input signals, for generating a plurality of logical product terms. A programmable sum array combines the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is included which selectively causes each of the product terms, the equivalent input signals, and the inverted input signals to have a predetermined logic state in response to at least one control signal.

REFERENCES:
patent: 3940740 (1976-02-01), Coontz
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4329685 (1982-05-01), Mahon et al.
Fujiwara et al., "A Design of Programmable Logic Arrays with Universal Tests", IEEE Transactions on Computers, Nov. 1981.
Daehn et al., "A Hardware Approach to Self-Testing of Large Programmable Logic Arrays", IEEE Transactions on Computer, Nov. 1981.
"The Effect of Untestable Faults in PLAs and a Design for Testability", IEEE Test Conference, Nov. 1980.

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