Programmable logic array with single clock dynamic logic

Details Programmable logic array with single clock dynamic logic Programmable logic array with single clock dynamic logic

1985-10-21

1988-04-26

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307469, 307481, 34082583, 364716, H03K 1716, H03K 19096, H03K 19173

Patent

active

047407212

ABSTRACT:
Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

REFERENCES:
patent: 3974366 (1976-08-01), Hebenstreit
"Principles of CMOS VLSI Design--A Systems Perspective" Weste and Eshraghian, Addison-Wesley Publishing 1985.
Weste, et al., "Principles of CMOS VLSI Design-A Systems Perspective", pp. 163-171; 203-221; 368-379; 418-419.
Penney et al., "MOS Integrated Circuits-Theory, Fabrication, Design and Systems Applications of MOS LSI", pp. 260-288.
Myers, et al. "A Design Style for VLSI CMOS", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 3, Jun. 1985, pp. 741-745.
Goncalves, et al., "NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures", IEEE Journal of Solid-State Circuits, pp. 261-266, vol. SC-18, No. 3, Jun. 1983.
May et al., "High Speed Static Programmable Logic Array in LOCMOS", IEEE Journal Solid-State Circuits, vol. SC-11, pp. 365-369, Jun. 1976.

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