Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-10-06
1990-01-16
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307443, 307469, 307481, 3072961, H03K 1704, H03K 19177
Patent
active
048945641
ABSTRACT:
A programmable logic array comprises an OR circuit (67) and an AND circuit (68). A voltage lower than a power-supply voltage is applied to product term lines (57-60) from a power supply portion (69) in response to conduction of p channel transistors (31-34) by a clock signal to be precharged, and a voltage lower than the power-supply voltage is applied to output lines (54, 55) from a power supply portion (70) in response to conduction of p channel transistors (39, 40) by the clock signal. Therefore, applied voltages of the product term lines and the output lines are lowered, so that responsibility of circuit is improved, whereby a programmable logic array with a high speed operation is obtained.
REFERENCES:
patent: 4467439 (1984-08-01), Rhodes
patent: 4831285 (1989-05-01), Gaiser
patent: 4833646 (1989-05-01), Turner
Gray, "Ground Buffer Circuit for Read-Only Memory Array", IBM T.D.B., vol. 24, No. 7A, Dec. 1981, pp. 3315-3316.
"Power Reduction Method for Static CMOS Programmable Logic Arrays (PLAS)" IBM T.D.B. vol. 30, No. 10, Mar. 1988, p. 247-248.
Hashizume Takeshi
Ohya Takashi
Sakashita Kazuhiro
Hudspeth David
Mitsubishi Denki & Kabushiki Kaisha
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