Programmable logic array with interfacial plane

Details Programmable logic array with interfacial plane Programmable logic array with interfacial plane

1989-02-27

1990-05-08

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307469, 307481, H03K 19177

Patent

active

049241184

ABSTRACT:
A programmable logic array has an interfacial plane between an AND plane and an OR plane for relaying the result of the AND operation to the OR plane, and the interfacial plane has intermediate nodes for the relaying functions which are simultaneously charged up to a high voltage level and selectively discharged to a low voltage level depending upon the result of the AND operation, wherein field effect transistors are provided for the selective discharging operation and simultaneously gated by a control signal line, so that only the gate capacitances of the field effect transistors are coupled to the control signal line, thereby improving the operation speed of the programmable logic array.

REFERENCES:
patent: 4661728 (1987-04-01), Kashimura
patent: 4687959 (1987-08-01), Eitrheim et al.
patent: 4697105 (1987-09-01), Moy
patent: 4740721 (1988-04-01), Chung et al.
patent: 4760290 (1988-07-01), Martinez
patent: 4764691 (1988-08-01), Jochem
patent: 4769562 (1988-09-01), Ghisio
patent: 4831285 (1989-05-01), Gaiser
patent: 4841174 (1989-06-01), Chung et al.

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