Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1985-08-12
1988-07-19
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307468, 307473, 364716, H03K 19177
Patent
active
047587466
ABSTRACT:
A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.sub.1 through O.sub.10) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.
REFERENCES:
patent: 3818252 (1974-06-01), Chiba et al.
patent: 3936812 (1976-02-01), Cox et al.
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4177452 (1979-12-01), Balasubramanian et al.
patent: 4267463 (1981-05-01), Mayumi
patent: 4422072 (1983-12-01), Cavlan
patent: 4488230 (1984-12-01), Harrison
patent: 4488246 (1984-12-01), Brice
patent: 4506341 (1985-03-01), Kalter et al.
patent: 4642487 (1987-02-01), Carter
Davis, "Inverted AND Array In PLA Structure"; IBM-TDB; vol. 25, No. 12, pp. 6488-6490; 5/1983.
Altera EP310 Erasable Programmable Logic Device Data Sheet, published in 1985 by Altera Corporation.
AmPAL22V10 Data Sheet, published in May, 1984 by Advanced Micro Devices Corporation.
Ricoh CMOS EPL Series 20A and 20B Data Sheets, published in Oct., 1985 by Ricoh.
"LSI Databook", published by Monolithic Memories, Inc. in 1985, pp. 5-41 to 5-80.
"PAL Programmable Array Logic Handbook", published by Monolithic Memories, Inc. in 1983, pp. 3-24 to 3-52.
Ricoh CMOS Electrically Programmable Logic Data Sheet (Japanese Language).
Birkner John
Chan Albert
Chan Andrew K. L.
Chua Hua T.
Hudspeth D. R.
Leeds Kenneth E.
MacPherson Alan H.
Miller Stanley D.
Monolithic Memories Inc.
LandOfFree
Programmable logic array with added array of gates and added out does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic array with added array of gates and added out, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic array with added array of gates and added out will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-598960