Programmable logic array, including an arrangement for invalidat

Details Programmable logic array, including an arrangement for invalidat Programmable logic array, including an arrangement for invalidat

1982-06-15

1985-04-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

364716, 371 10, G06F 1120, G06F 1122, G11C 2900

Patent

active

045118124

ABSTRACT:
A programmable logic array comprises an AND array for producing AND term outputs on a plurality of AND term lines, an OR array which receives the AND term output of the AND array as inputs thereto, and an AND term disregarding array connected to the AND term lines to selectively invalidate the AND term outputs. The AND term disregarding array functions to disregard one of the AND terms on which a program defect is present.

REFERENCES:
patent: 3654610 (1972-04-01), Sander et al.
patent: 3681757 (1972-08-01), Allen et al.
patent: 4032894 (1977-06-01), Williams
patent: 4051354 (1977-09-01), Choate
patent: 4380811 (1983-04-01), Gotze et al.
Chu et al., "Redundant Bit Line Decode Circuit", IBM Tech. Discl. Bull., vol. 18, No. 6, pp. 1777-1778, Nov. 1975.

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