Programmable logic array in ECL technology

Details Programmable logic array in ECL technology Programmable logic array in ECL technology

1983-04-25

1985-03-19

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

045063630

ABSTRACT:
A programmable logic array, constructed in emitter coupled logic technology, may be tested in its non-programmed condition. Diodes are located between all product terminal lines and first test terminals on the semiconductor chip as they are disposed between all sum term lines and a second test terminal. Furthermore, each input line of the sum matrix is respectively connected by way of a diode to the inverting output of a respective different input amplifier. When the sum matrix exhibits more input lines than there are input amplifiers, the connection is repeated cyclically. In this case, the sum matrix is divided into sub-matrices whose mutually corresponding sum term lines are linked by way of logic elements.

REFERENCES:
patent: 3958110 (1976-05-01), Hong et al.
patent: 4225957 (1980-09-01), Doty, Jr. et al.
patent: 4380811 (1983-04-01), Gotze et al.
patent: 4410987 (1983-10-01), Ptasinski et al.
patent: 4418410 (1983-11-01), Goetze et al.
patent: 4429388 (1984-01-01), Fukushima et al.
patent: 4435805 (1984-03-01), Hsieh et al.
patent: 4461000 (1984-07-01), Young
Kazmi, S., "Design Prototypes Quickly with Programmable Arrays", Electronic Design, Feb. 19, 1981, pp. 121-124.
Patent Abstracts of Japan, (54-56155 Appl. No.), 55-147833, Nov. 18, 1980.

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