Programmable logic array device with random access memory config

Details Programmable logic array device with random access memory config Programmable logic array device with random access memory config

1999-11-19

2000-09-12

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

36518901, 36523002, 36523006, 36523008, 36518902, 326 40, 326 39, 326 41, H03K 1977, G11C 800

Patent

active

061187208

ABSTRACT:
A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3849638 (1974-11-01), Greer
patent: 4740917 (1988-04-01), Denis et al.
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 4975601 (1990-12-01), Steele
patent: 5027011 (1991-06-01), Steele
patent: 5099150 (1992-03-01), Steele
patent: 5121006 (1992-06-01), Pedersen
patent: 5128559 (1992-07-01), Steele
patent: 5144582 (1992-09-01), Steele
patent: 5270587 (1993-12-01), Zagar
patent: 5302865 (1994-04-01), Steele et al.
patent: 5362999 (1994-11-01), Chiang
patent: 5383146 (1995-01-01), Threewitt
patent: 5386155 (1995-01-01), Steele et al.
patent: 5408434 (1995-04-01), Stansfield
patent: 5450608 (1995-09-01), Steele
patent: 5473267 (1995-12-01), Stansfield
patent: 5532957 (1996-07-01), Malhi
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5557218 (1996-09-01), Jang
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5559747 (1996-09-01), Kasamizugami et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5757207 (1998-05-01), Lytle et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 5828229 (1998-10-01), Cliff et al.
patent: 6020759 (2000-02-01), Heile
C. Barre, "L'utilisation du FPLA; Evaluez les Applications d'un Composant Puissant qui Peut se Reveler tres Economique", Electronique & Applications Industrielles, EAI 250, Apr. 1, 1978, pp. 21-25.
D. Bursky, "Combination RAM/PLD Opens New Application Options", Electronic Design, May 23, 1991, pp. 138-140.
"iFX8160 10ns FLEXlogic FPGA with SRAM Option; Advance Information", Intel Corporation, Oct. 1993, pp. 2-47 through 2-56.
T. K-K. Ngai, "AN SRAM-Programmable Field-Reconfigurable Memory", Master of Applied Science degree thesis submitted to the Department of Electrical Engineering of the University of Toronto, 1994.
A. Stansfield et al., "The Design of a New FPGA Architecture", Proceedings Field Programmable Logic (FPL) 1995, Springer Lecture Notes in Computer Science 975, pp. 1-14.
A. Kaviani et al., "Hybrid FPGA Architecture", Proceedings 4th International Symposium on FPGAs (FPGA 96), Feb. 1996.
Reddy, S. et al. "A High Density Embedded Array Programmable Logic Architecture", IEEE 1996 Custom Integrated Circuits Conference, May 5, 1996, pp. 251-254.
Brown, S. et al. "FPGA and CPLD Architectures: A Tutorial", IEEE Design & Test of Computers, Jun. 1, 1996, pp. 42-57.
Nelson, R. "Embedded memory enhances programmable logic for complex, compact designs", Electrical Design News (EDN), vol. 41, No. 23, Nov. 7, 1996, pp. 91, 92, 94, 96, 98, 100-102, and 106.
"Altera Enables System-Level Integration with Raphael Family of Embedded PLDs", Altera Corporation, San Jose, California, Aug. 31, 1998.
"Apex 20K Programmable Logic Device Family; Advance Product Brief", Altera Corporation, San Jose, California, Oct. 1998, pp. 1, 2, and 9.
"Altera Unveils New Name for Raphael: Advanced Programmable Embedded Matrix (APEX)", Altera Corporation, San Jose, California, Oct. 7, 1998.
"Apex 20K Device Family; The Embedded PLD Family for System-Level Integration", Altera Corporation, San Jose, California, after Aug. 31, 1998.
"Apex 20K Device Family; Breakthrough MultiCore Architecture", Altera Corporation, San Jose, California, after Aug. 31, 1998.
F. Heile et al., "Hybrid Product Term and LUT Based Architecture Using Embedded Memory Blocks", Proceedings of FPGA 1999 Conference, Feb. 21-23, 1999, Monterey, California.
"Next Generation FPGAs; Xilinx Next Generation FPGAs Deliver World-Class Performance", The Power of Innovation 1997, Xilinx, Inc., San Jose, CA. p. 7-7.

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