Programmable logic array

Details Programmable logic array Programmable logic array

1986-06-05

1988-08-23

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365201, 34082583, 371 21, 364715, G11C 700, G11C 2900

Patent

active

047665696

ABSTRACT:
A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.

REFERENCES:
patent: 4041459 (1977-08-01), Horninger
patent: 4490812 (1984-12-01), Guterman
patent: 4503387 (1985-03-01), Rutledge et al.
patent: 4625311 (1986-11-01), Fitzpatrick et al.
patent: 4631695 (1986-12-01), Kozlik
"A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version," K. Horninger, IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, pp. 331-336, Oct. 1975.
"An Electrically Alterable PLA for Fast Turnaround-Time VLSI Development Hardware," Wood et al., IEEE Journal of Solid State Circuits, vol. SC-16, No. 5, pp. 570-577, Oct. 1981.
"Testing the EEPROM on the MC68HC11," by Alex Shaw and Clyde Browning, Paper p. 5, 1985 International Test Conference.
Product Description of Field Programmable Logic Array Devices from the Bipolar Memory Division of Signetics, Date Jan. 1983.
"Field-PLAs Simplify Logic Designs," by N. Cavlan and R. Cline, Electronic Design, Sep. 1, 1975.
"Introduction to VLSI Systems," by Carver Mead and Lynn Conway, 1980, pp. 79-82.

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