Programmable lock detector and corrector

Details Programmable lock detector and corrector Programmable lock detector and corrector

2005-11-29

2005-11-29

Shingleton, Michael B (Department: 2817)

Oscillators

Polyphase output

C331S016000, C331S018000, C331SDIG002, C331S025000, C327S158000, C327S161000, C327S159000, C327S160000, C327S156000, C327S276000

Reexamination Certificate

active

06970047

ABSTRACT:
An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

REFERENCES:
patent: 5815016 (1998-09-01), Erickson
patent: 6259290 (2001-07-01), Takada et al.
patent: 6504408 (2003-01-01), von Kaenel
patent: 6794944 (2004-09-01), Hirai
patent: 2002314409 (2002-10-01), None
Greenfield et al. “Using Microprocessors and Microcomputers: The 6800 Family”, John Wiley & Sons, Inc. 1981, p. 10.
“CMOS DLL Based 2V, 2.3ps Jitter, 1GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,” by David J. Foley,Studen Member, IEEE, andMichael P. Flynn,Senior Member, IEEE.IEEE Journal of solid state circuits vol. 36 Issue 3 Mar. 2001 pp 417-423.

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