Programmable linear feedback shift register timeout mechanism

Details Programmable linear feedback shift register timeout mechanism Programmable linear feedback shift register timeout mechanism

1996-06-21

1997-03-04

Heckler, Thomas M.

G06F 114

Patent

active

056088973

ABSTRACT:
A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.

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IBM Technical Disclosure Bulletin, vol. 28, No. 2, Jul. 1985 "Bit-Pushing Approach to VLSI Circuit Self-Testing", pp. 676-679.

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