Programmable leakage current offset for phase locked loop

Details Programmable leakage current offset for phase locked loop Programmable leakage current offset for phase locked loop

2002-08-29

2003-05-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000

Reexamination Certificate

active

06570421

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system (
10
) has, among other components, a microprocessor (
12
), one or more forms of memory (
14
), integrated circuits (
16
) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (
19
), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (
10
).
In order to properly accomplish such tasks, the computer system (
10
) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (
18
) generates a system clock signal (referred to and known in the art as “reference clock” and shown in
FIG. 1
as SYS_CLK) to various parts of the computer system (
10
). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor (
12
) and the other components of the computer system (
10
) use a proper and accurate reference of time.
One component used within the computer system (
10
) to ensure a proper reference of time among the system clock signal and a microprocessor clock signal, i.e., “chip clock signal” or CHIP_CLK, is a type of clock generator known as a phase locked loop (PLL) (
20
). The PLL (
20
) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to the system clock signal. Referring to
FIG. 1
, the PLL (
20
) has as its input the system clock signal, which is its reference signal, and outputs a chip clock signal (shown in
FIG. 1
as CHIP_CLK) to the microprocessor (
12
). The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL (
20
). This relationship between the phases and frequencies of the system clock signal and chip clock signal ensures that the various components within the microprocessor (
12
) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (
20
), however, the operations within the computer system (
10
) become non-deterministic.
FIG. 2
shows a block diagram of a typical PLL (
200
). The PLL (
200
) includes a PLL core (
250
), buffers (
212
,
214
,
216
,
218
), and a feedback loop signal (
221
) on a feedback loop path. The buffers (
212
,
214
) increase the drive strength of an output clock signal (
215
) to supply other circuits of the microprocessor (
12
in
FIG. 1
) with a chip clock signal (
217
). The buffers (
216
,
218
) buffer the chip clock signal (
217
) to additional circuits of the microprocessor (
12
in FIG.
1
). The time delay created by the buffers (
212
,
214
,
216
,
218
) is accounted for in the feedback signal (
221
) that is supplied to the PLL core (
250
).
The PLL core (
250
) is designed to output the chip clock signal (
217
), which is a multiple of the system clock signal (
201
). When the PLL is in “lock,” the chip clock signal (
217
) and system clock signal (
201
) maintain a specific phase relationship. To allow different multiplication ratios, the PLL core (
250
) may use several “divide by” circuits. A “divide by” circuit reduces the frequency of the input to the “divide by” circuit at its output by a specified factor. For example, the PLL core (
250
) uses a divide by A circuit (
220
) with the system clock signal (
201
), a divide by C circuit (
222
) with a voltage-controlled oscillator (
210
) output signal (
213
), and a divide by B circuit (
224
) with the feedback loop signal (
221
).
A phase-frequency detector (
202
) aligns the transition edge and frequency of a clock A signal (
221
) and a clock B signal (
223
). The phase-frequency detector (
202
) adjusts its output frequency in order to zero any phase and frequency difference between the clock A signal (
221
) and the clock B signal (
223
). The phase-frequency detector (
202
) produces signals that control charge pumps (
204
,
234
). The phase-frequency detector (
202
) controls the charge pumps (
204
,
234
) to increase or decrease their output using control signals up (
203
) and down (
205
). The charge pump (
204
) adds or removes charge from a capacitor C
1
(
206
) that changes the voltage potential at the input of a bias-generator (
208
). The capacitor (
206
) is connected between a power supply V
DD
and a voltage potential on a control signal V
CTRL
(
207
). The charge pump (
234
) adds or removes charge from a bias voltage V
BP
(
209
) of a bias-generator (
208
).
The bias-generator (
208
) produces bias voltages V
BP
(
209
) and V
BN
(
211
) in response to the voltage potential on the control signal (
207
). The PLL core (
250
) may be self-biased by adding the charge pump (
234
) to the bias-generator (
208
) bias voltage V
BP
(
209
). The addition of a second charge pump (
234
) allows the removal of a resistor in series with the capacitor (
206
). A voltage-controlled oscillator (
210
) produces an output signal (
213
) that has a frequency related to the bias voltages V
BP
(
209
) and V
BN
(
211
).
The “divide by” circuits (
220
,
222
,
224
) determine the frequency multiplication factor provided by the PLL core (
250
). The addition of “divide by” circuits (
220
,
222
,
224
) enables the PLL core (
250
) to multiply the system clock signal (
201
). Multiplying the system clock signal (
201
) is useful when the chip clock signal (
217
) must have a higher frequency than the system clock signal (
201
).
For example, during normal operation, the variables A and C may both be set to one in the divide by A circuit (
220
) and divide by C circuit (
222
), respectively. The variable B may be set to 10 in the divide by B circuit (
224
). The phase-frequency detector (
202
) aligns the transition edge and frequency of the clock A signal (
221
) and the clock B signal (
223
). The phase-frequency detector (
202
) adjusts PLL core (
250
) output clock signal (
215
) frequency in order to zero any phase and frequency difference between the clock A signal (
221
) and the clock B signal (
223
). Because the clock B signal (
223
) has a divide by B circuit (
224
) that reduces its input frequency by 10, the phase-frequency detector (
202
) adjusts the voltage-controlled oscillator (
210
) output signal (
213
) to a frequency 10 times greater than the clock A signal (
221
). Accordingly, the chip clock signal (
217
) is 10 times higher in frequency than the system clock signal (
201
).
The power consumption of a microprocessor is of concern. Reducing the frequency of the chip clock signal (
217
) reduces the switching rate of other circuits in the microprocessor (
12
in FIG.
1
). A low power mode may be entered when there is no activity in the microprocessor for an extended period of time. A slower switching rate typically reduces the power consumption of a microprocessor (
12
in FIG.
1
).
A change in the frequency of the chip clock signal (
217
) is accomplished by changing the ratio in the divide by circuits (
220
,
222
,
224
). For example, during reduced power operation, the variable A may be set to 16 in the divide by A circuit (
220
); the variable B may be set to 5 in the divide by B circuit (
224
); and the variable C may be set to 32 in the divide by C circuit (
222
). In this example, the frequency of the chip clock signal (
217
) is {fraction (5/16)} times the system clock signal (
201
). Also, the phase-frequency detector (
202
) updates 16 times less frequently compared to the non-reduced power example above.
Proper operation of the microprocessor (
12
shown in
FIG. 1
) depends on the PLL (
200
) maintaining a constant phase and frequency relationship between the system clock signal (
201
) and the chip clock signal (
217
).
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a clock path arranged to carry a clock signal; a power supply

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