Programmable interval timer with lock means

Details Programmable interval timer with lock means Programmable interval timer with lock means

1985-02-04

1987-11-10

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307517, 371 62, H03K 519, H03M 1300

Patent

active

047059702

ABSTRACT:
A programmable interval timer (100) for generating an error signal when a timing signal is received outside a predetermined time frame. The timer includes a timer circuit (104) having programmable minimum and maximum timing intervals for determining the predetermined time frame. These timing intervals are programmed into the timer circuit in response to data input signals indicative of the timing intervals from, for example, a microprocessor. The timer circuit generates one output signal when the time interval between two consecutively received timing signals is less than the minimum timing interval. Another output signal is generated when the time interval is greater than the maximum timing interval. An error signal latch generates the error signal when it receives either one of the two timer circuit output signals. Also included is a lock circuit (102) for preventing the timer circuit from responding to any data input signals after the first timing signal is received. Lastly, an indicator latch (103) is also provided to indicate to, for example, a central processing unit that an error signal has been sent to the microprocessor. A reset signal from the central processing unit resets the indicator latch and unlocks the lock circuit to reprogram the minimum and maximum timing intervals.

REFERENCES:
patent: 4083366 (1978-04-01), Gombrich et al.
patent: 4161787 (1979-07-01), Groves et al.
patent: 4171471 (1979-10-01), Boyles
patent: 4438402 (1984-03-01), Cullen et al.
patent: 4455661 (1984-06-01), Qureshi
patent: 4524291 (1985-06-01), Lehning
patent: 4531223 (1985-07-01), Ashida

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