Programmable interrupt controller

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G06F 946

Patent

active

051014971

ABSTRACT:
A computer system including a programmable interrupt controller wherein individual interrupt levels can be programmed to receive edge or level sensed interrupt signals. The controller includes a programmable register for storing the interrupt level designations for each interrupt level and associated interrupt recognition logic.

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IBM Technical Disclosure Bull., vol. 28 No. 11, Apr. 1986, pp. 4971-4972, "Hardware Interrupt Vectoring Circuit For Non-Compatible Peripheral".
Manual Excerpt: "8259A/8259A-2/8259A-8 Programmable Interrupt Controller", Microsystems Components Handbook, vol. 1, 1984, Intel Corp. pp. 2-120-2-127.
IBM Technical Disclosure Bulletin, vol. 29, No. 6, No. 6, Nov. 1986, pp. 2380-2381, "Interrupt Sharing For Personal Computer".
IBM Technical Disclosure Bulletin, vol. 25, No. 9, pp. 4651-4655, G. Davis, "Signature Analysis Testing of the Interrupt Controller" . . . .
Intel Corp., Microprocessor and Peripheral Handbook, vol. 1, pp. 2-271 to 2-314, 1987.
IBM Corp. Personal System/2 Model 80 Technical Reference, First Ed., Apr. 1987, pp. 2-63 to 2-65.

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