Programmable interconnect structures and programmable integrated

Details Programmable interconnect structures and programmable integrated Programmable interconnect structures and programmable integrated

1992-07-28

1994-11-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437922, H01L 21283

Patent

active

053626761

ABSTRACT:
An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation. The bottom electrodes of the antifuses are connected to the first-metal contacts. The overall capacitance associated with the antifuses is low, and hence the circuit is fast.

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