Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1998-05-08
2000-08-01
Martin-Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
257 50, 438467, 438600, H01L 2900
Patent
active
060970774
ABSTRACT:
Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
REFERENCES:
patent: 3675090 (1972-07-01), Neale
patent: 3792319 (1974-02-01), Tsang
patent: 4424578 (1984-01-01), Miyamoto
patent: 4441167 (1994-04-01), Principi.
patent: 4458297 (1984-07-01), Stopper et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4519849 (1985-05-01), Korsch et al.
patent: 4569120 (1986-02-01), Stacy et al.
patent: 4569121 (1986-02-01), Lim et al.
patent: 4590589 (1986-05-01), Gerzberg
patent: 4641420 (1987-02-01), Lee
patent: 4651409 (1987-03-01), Ellsworth et al.
patent: 4751197 (1988-06-01), Wills
patent: 4758745 (1988-07-01), El Gammal et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4847732 (1989-07-01), Stopper et al.
patent: 4857774 (1989-08-01), El-Ayat et al.
patent: 4862243 (1989-08-01), Welch et al.
patent: 4873459 (1989-10-01), El Gammal et al.
patent: 4882611 (1989-11-01), Blech et al.
patent: 4898841 (1990-02-01), Ho
patent: 4910417 (1990-03-01), El Gammal et al.
patent: 4914055 (1990-04-01), Gordon et al.
patent: 4922319 (1990-05-01), Fukushima
patent: 4933898 (1990-06-01), Gilberg et al.
patent: 4943538 (1990-07-01), Mohsen
patent: 4949084 (1990-08-01), Schwartz et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 5011791 (1991-04-01), Mastroianni
patent: 5066612 (1991-11-01), Ohba et al.
patent: 5093711 (1992-03-01), Hirakawa
patent: 5100827 (1992-03-01), Lytle
patent: 5106773 (1992-04-01), Chen et al.
patent: 5120679 (1992-06-01), Boardman et al.
patent: 5181096 (1993-01-01), Farouhi
patent: 5196724 (1993-03-01), Gordon et al.
patent: 5233217 (1993-08-01), Dixit et al.
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5319238 (1994-06-01), Gordon et al.
patent: 5362676 (1994-11-01), Gordon et al.
patent: 5557136 (1996-09-01), Gordon et al.
patent: 5701027 (1997-12-01), Gordon et al.
Cook, Brian, et al., "Amorphous Silicon Antifuse Technology for Bipolar PROMs", 1986 Bipolar Circuits and Technology Meeting, IEEE 1986, pp./ 99-100.
Joshi, R.V., et al., "Low-Resistance Submicron CVD W Interlevel Via Plugs on Al-Cu-Si", Jun. 12-13, 1989 VMIC Conference, IEEE 1989, pp. 113-121.
Ohba, T. et al., "Selective and Blanet Tungsten Interconnection and its Suitability for 0.2 Micron ULSI", Jun. 12-13, 1990 VMIC Conference, IEEE 1990, pp. 226-232.
Hamdy, E., et al.,"Dielectric Based Antifuse For Logic and Memory ICs", IEDM 1988, pp. 786-789.
Moriya, T., et al., "A Planar Metallization Process-Its Application to Tri-Level Aluminum Interconnection", 83 IEDM 550-553 (IEEE 1983).
van Laarhoven, J.M.F.G., et al., "A Novel Blanket Tungsten Etchback Scheme", Jun. 12-13, 1989 VMIC Conference, IEEE 1989, pp. 129-135.
Adams, A.C., "Plasma Deposition of Inorganic Films", Solid State Technology, Apr. 1983, pp. 135-139.
Broom, R.F., et al., "Discretionary Information Method for Integrated Circuits", IBM Technical Disclosure Bulletin, vol. 14, No. 11 (Apr. 1972) pp. 3549-3550.
Actel Corporation "Antifuse Backgrounder"(Tsantes & Associates, Sunnyvale, CA, Nov. 1991), pp. 1-10.
Gordon Kathryn E.
Wong Richard J.
Martin-Wallace Valencia
QuickLogic Corporation
Shenker Michael
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