Programmable interconnect or cell using silicided MOS transistor

Details Programmable interconnect or cell using silicided MOS transistor Programmable interconnect or cell using silicided MOS transistor

1989-03-31

1991-05-28

James, Andrew J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 2312, 357 72, 365104, 365182, H01L 2910

Patent

active

050198785

ABSTRACT:
A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

REFERENCES:
patent: 4467520 (1984-08-01), Shiotari
patent: 4507757 (1985-03-01), McElroy
patent: 4819043 (1989-04-01), Yazawa et al.
patent: 4837181 (1989-06-01), Galbiati et al.
patent: 4847808 (1989-07-01), Kobatake
Minato et al., "High Performance 4k Dynamic RAM Fabricated with Short Channel MOS Technology," 1978, Japanese Journal of Applied Physics, vol. 17, Supplement 17-1, pp. 65-69.

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