Programmable interconnect for semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S750000, C257S774000, C257S776000

Reexamination Certificate

active

06559544

ABSTRACT:

BACKGROUND OF THE INVENTION
Taking a semiconductor device from a prototype stage to a volume production manufacturing stage often requires multiple revisions of the device with each revision correcting various deficiencies in the device's operation. Such revisions typically involve changes made to one or more metal layers in order to correct errors or modify the existing circuits. Such changes are often referred to as metal mask changes or metal spins. In order to implement such changes, a new metal mask layer is required to be created. Creating new metal masks can add considerable expense during the development of a new semiconductor product. Accordingly, there is a need to provide a mask, which maximizes the ability of a device to be made functional, and thereby minimizing the number of new masks required.
SUMMARY OF THE INVENTION
The present invention provides to a method and structure for selectively programming interconnections between a plurality of metal segments in a multilayer semiconductor devices. These metal programmable segments can be used for programming respective bits of a semiconductor device identification number by providing a plurality of possible changes for each bit of an identification number. The metal programmable layers can also be used for selectively adjusting characteristics of an electronic component such as a resistor or capacitor on the semiconductor device.
In accordance with this invention there is provided a structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.


REFERENCES:
patent: 6248658 (2001-06-01), Buynoski
patent: 6291305 (2001-09-01), Huang et al.
patent: 6222275 (2002-04-01), Keeth
patent: 6392253 (2002-05-01), Saxena
patent: 6424028 (2002-07-01), Dickinson
patent: 2002/0063249 (2002-05-01), Sloman
patent: 2002/0105406 (2002-08-01), Llu et al.
patent: 2002/0158321 (2002-10-01), Duesman et al.
patent: 2002/0172820 (2002-11-01), Majumdar et al.

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