Programmable interconnect architecture having interconnects disp

Details Programmable interconnect architecture having interconnects disp Programmable interconnect architecture having interconnects disp

1990-08-01

1992-07-21

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307468, 3073032, 357 45, H03K 19177

Patent

active

051325713

ABSTRACT:
A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second the third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

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Kurzberg & Yotta, "Channel Assignment for Chip Wiring", IBM T.D.B., vol. 26, No. 3A, Aug. 1983, pp. 934-936.
Freeman, "User--programmable gate arrays", IEEE Spectrum, Dec. 1988, pp. 32-35.

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