Programmable interconnect architecture

Details Programmable interconnect architecture Programmable interconnect architecture

1991-01-15

1992-12-15

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3074651, H03K 19077

Patent

active

051720140

ABSTRACT:
A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected.

REFERENCES:
patent: 3816725 (1974-06-01), Greer
patent: 3818452 (1974-06-01), Greer
patent: 3849638 (1974-11-01), Greer
patent: 3987287 (1976-10-01), Cox et al.
patent: 4293783 (1981-10-01), Patil
patent: 4433331 (1984-02-01), Kollaritsch
patent: 4642487 (1987-02-01), Carter
patent: 4706216 (1987-11-01), Carter
patent: 4713557 (1987-12-01), Carter
patent: 4758985 (1988-07-01), Carter
patent: 4772811 (1988-09-01), Fujioka et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5003200 (1991-03-01), Sakamoto
patent: 5019736 (1991-05-01), Furtek
John Wawrzynek and Carver Mead, A VLSI Architecture for Sound Synthesis, Oct. 10, 1984, pp. 9 and 10.
D. Greer, An Associative Logic Matrix, J. of Solid State Circuits, vol. SC-11, No. 5, Oct., 1976, pp. 679-691.
J. I. Raffel, On the Use of Nonvolatile Programmable Links for Restructurable VLSI, Caltech Conference on VLSI, Jan., 1979 pp. 95-104.
S. Patil and T. Welch, A programmable Logic Approach for VLSI, IEEE Trans. on Computers, vol. c-28, No. 9, Sep., 1979, pp. 594-601.
R. Wood, A High Density Programmable Logic Array Chip, IEEE Trans. on Computers, vol. c-28, No. 9, Sep. 1979, pp. 602-608.
R. Wood, Y. Hsieh, C. Price, and P. Wang, An Electrically Alterable PLA for East Turnaround-Time VLSI Development Hardware, IEEE J. of Solid-State Circuits, vol. SC-16, No. 5, Oct., 1981, pp. 570-577.

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