Programmable interconnect architecture

Details Programmable interconnect architecture Programmable interconnect architecture

1992-12-18

1995-05-09

Trans, Vincent N.

Boots, shoes, and leggings

364488, 34082583, H03K 17693

Patent

active

054146380

ABSTRACT:
A programmable interconnect system includes a two-level hierarchal structure of programmable interconnect chips on a circuit board. The first-level, or "local", interconnect chips are connected to user components. A plurality of second-level, or "global", interconnect chips interconnect the local interconnect chips so that every local chip is connected to every global chip. Such a system allows connecting any pin of any user component to any other pin of any user component by a conductive path passing through at most three interconnect chips. A large number of such paths are provided even in embodiments with a large number of interconnect chips.

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FPCB AXB-GP2 General Purpose Field Programmable Circuit Board, Preliminary Data Sheet, Aptix Corporation, Aug. 1992, v1.0.
R. Guo et al., A 1024 Pin Universal Interconnect Array with Routing Architecture, Proceedings IEEE 1992 Custom Integrated Circuit Conference, may 1992, pp. 4.5.1. through 4.5.4.

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