Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2005-12-06
2005-12-06
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S119000, C702S123000, C714S724000, C714S725000
Reexamination Certificate
active
06973405
ABSTRACT:
A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The verification agent interacts with the module under test, including sending signals to the module under test and generating results based on the interaction. The code causes the processor to receive the results and compare the results with expected values. The module under test may be deemed to operate properly if the actual results match the expected values.
REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4855669 (1989-08-01), Mahoney
patent: 5072418 (1991-12-01), Boutaud et al.
patent: 5142625 (1992-08-01), Nakai
patent: RE34363 (1993-08-01), Freeman
patent: 5274570 (1993-12-01), Izumi et al.
patent: 5311114 (1994-05-01), Sambamurthy et al.
patent: 5339262 (1994-08-01), Rostoker et al.
patent: 5347181 (1994-09-01), Ashby et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5457410 (1995-10-01), Ting
patent: 5473267 (1995-12-01), Stansfield
patent: 5500943 (1996-03-01), Ho et al.
patent: 5504738 (1996-04-01), Sambamurthy et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5543640 (1996-08-01), Sutherland et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5552722 (1996-09-01), Kean
patent: 5574930 (1996-11-01), Halverson, Jr. et al.
patent: 5574942 (1996-11-01), Colwell et al.
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5600845 (1997-02-01), Gilson
patent: 5652904 (1997-07-01), Trimberger
patent: 5671355 (1997-09-01), Collins
patent: 5705938 (1998-01-01), Kean
patent: 5732250 (1998-03-01), Bates et al.
patent: 5737631 (1998-04-01), Trimberger
patent: 5740404 (1998-04-01), Baji
patent: 5742179 (1998-04-01), Sasaki
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5748979 (1998-05-01), Trimberger
patent: 5752035 (1998-05-01), Trimberger
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5809517 (1998-09-01), Shimura
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5874834 (1999-02-01), New
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5892961 (1999-04-01), Trimberger
patent: 5914616 (1999-06-01), Young et al.
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 5933023 (1999-08-01), Young
patent: 5970254 (1999-10-01), Cooke et al.
patent: 6011407 (2000-01-01), New
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6026481 (2000-02-01), New et al.
patent: 6096091 (2000-08-01), Hartmann
patent: 6108806 (2000-08-01), Abramovici et al.
patent: 6154051 (2000-11-01), Nguyen et al.
patent: 6163166 (2000-12-01), Bielby et al.
patent: 6172990 (2001-01-01), Deb et al.
patent: 6178533 (2001-01-01), Chang
patent: 6178541 (2001-01-01), Joly et al.
patent: 6181163 (2001-01-01), Agrawal et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6247151 (2001-06-01), Poisner
patent: 6272451 (2001-08-01), Mason et al.
patent: 6272588 (2001-08-01), Johnston et al.
patent: 6279045 (2001-08-01), Muthujumaraswathy et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6301696 (2001-10-01), Lien et al.
patent: 6343207 (2002-01-01), Hessel et al.
patent: 6356987 (2002-03-01), Aulas
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6412046 (2002-06-01), Sharma et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6578174 (2003-06-01), Zizzo
patent: 6604228 (2003-08-01), Patel et al.
patent: 6615167 (2003-09-01), Devins et al.
patent: 2001/0049813 (2001-12-01), Chan et al.
patent: 2003/0009712 (2003-01-01), Lukanc
patent: 0315275 (1989-10-01), None
patent: 0 905 906 (1999-03-01), None
patent: 1 235 351 (2002-08-01), None
patent: WO 93 25968 (1993-12-01), None
Sayfe Kiaei et al., “VLSI Design of Dynamically Reconfigurable Array Processor-DRAP,” IEEE, Feb. 1989, pp. 2484-2486, 2488, V3.6, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Vason P. Srini, “Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC,” IEEE, May 1991, pp. 309-311, 313, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
G. Maki et al., “A Reconfigurable Data Path Processor,” IEEE, Aug. 1991, pp. 18-4.1 and 18-4.3 IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jacob Davidson, “FPGA Implementation of Reconfigurable Microprocessor,” IEEE, Mar. 1993, pp. 3.2.1-3.2.3 IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al. “Beyond Superscaler Using FPGA's,” IEEE, Apr. 1993, pp. 486-488, 490, IEEE, 3 Park Avenue, 17th floor, New York, NY 10016-5997.
P.C. French et al., “A Self-Reconfiguring Processor,”; IEEE, Jul. 1993, pp. 50-59, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al., “Spyder: A Reconfigurable VLIW Processor Using FPGA's,” IEEE, Jul. 1993, pp. 17-24, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Michael I. Wirthlin et al., “The Nano Processor: A Low Resource Reconfigurable Processor,” IEEE, Feb. 1994, pp. 23-30, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
William S. Carter “The Future of Programmable Logic and Its Impact on Digital System Design,” Apr. 1994, IEEE, pp. 10-16, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Andre′ Dehon, “DPGA-Coupled Microprocessor: Commodity ICs for the Early 21st Century,” IEEE, Feb. 1994, pp. 31-39, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Osama T. Albaharna, “Area & Time Limitations of FPGA-Based Virtual Hardware,” IEEE, Apr. 1994, pp. 184-185, 186, 187, 188, 189, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx, Inc.,“The Programmable Logic Data Book,” 1994, Revised 1995, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124, 17 pages.
Xilinx, Inc.,“The Prgrammable Logic Data Book,” 1994, revised 1995, pp 2-109 to 2-117, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc.,“The Programmable Logic Data Book,” 1994, Revised 1995, pp 2-9 to 2-18; 2-187 to 2-199, Xilinx Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc.“The Programmable Logic Data Book,” 1994, Revised 1995, pp 2-107 to 2-108, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Christian Iseli et al., “AC++ Compiler For FPGA Custom Execution Units Synthesis,” 1995, pp. 179-179, IEEE, 3 PARK Avenue, 17th Floor, New York, NY 10016-5997.
International Business Machines“POWERPC 405 Embedded Processor Core User Manual,” 1996, 5TH Ed., pp. 1-1 TO X-16, International Business Machines, 1580 rout 52, Bldg. 504 Hopewell Junction, NY 12533-6531, no month.
Yamin Li et al., “AIZUP-A Pipelined Processor Design & Implementation on Xilinx FPGA Chip,” IEEE, Sep. 1996, pp 98-106, 98-106, IEEE, 3 Park Avenue, 17th Floor New York, NY 10016-5997.
Ralph D. Wittig et al., ONECHIP: An FPGA Processor With Reconfigurable Logic, Apr 17, 1996, pp 126-135, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx, Inc.,“The Programmable Logic Data Book,” Jan. 27, 1999, Ch. 3, pp 3-1 TO 3-50, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
William B. Andrew et al., “A Field Programmable System Chip Which Combines FPGA & ASIC Circuitry,” IEEE, May 16, 1999, pp. 183-186, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx Inc.,“The Programmable Logic Data Book,” 2000, Ch. 3 pp 3-1 TO 3-117, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, no month.
Xilinx, Inc.,“The Programmable Logic Data Book,” 2000, Ch 3, pp 3-7 TO 3-17; 3-76 TO 3-87, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
International Business Machines,“Processor Local Bus”Architecture Specifications, 32-Bit Implementation, Apr. 2000, First Edition, V2.9, pp. 1-76, IBM Corporation, Department H83A, P.O. Box 12195, Research Triangle Park, NC 27709.
Xilinx, In
Chan H. C.
Kanzaki Kim
Maunu LeRoy D.
Wachsman Hal
Xilinx , Inc.
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