Programmable integrated logic network having bipolar and MOS tra

Details Programmable integrated logic network having bipolar and MOS tra Programmable integrated logic network having bipolar and MOS tra

1990-09-26

1992-02-04

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, H03K 19177

Patent

active

050862405

ABSTRACT:
Each programming point (11) of the programmable logic network (10) according to the invention is made with a field effect transistor (N1), the gate and drain of which are connected respectively to the input (Lx) and output (Ly) lines, and the source of which is connected both to the reference potential, via the drain-to-source path of a second field effect transistor (N2), the gate of which is connected to the output line (Ly), and to the base of a bipolar transistor Q, the emitter-to-collector path of which is disposed between the ground and output lines. A network according to the invention has an increased operating speed and can be used in a read-only memory or in PLA circuits.

REFERENCES:
patent: 4409499 (1983-10-01), Zapisek et al.
patent: 4725745 (1988-02-01), Kondo et al.
patent: 4798977 (1989-01-01), Sakui et al.
IBM Technical Disclosure Bulletin, vol. 24, No. 5, Oct. 1981, pp. 2424-2425, New York, T. Winlow.
IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, pp.2957-2985, New York, G. J. Kelly et al.
IBM Technical Disclosure Bulletin, vol. 26, No. 11, Apr. 1984, pp. 5835-5837, New York, M. Cases et al.
VLSI Design, Dec. 1983, pp. 56-63, J. A. Sutton, "The 80C86 CMOS Design from the nMos Architecture".

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