Programmable integrated circuit output pad

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364490, 3072961, H03L 700

Patent

active

053372549

ABSTRACT:
A system is described that includes an integrated circuit chip having output paths connected to a network whose electrical of capacitance characteristics can vary. The system includes a circuit for adjusting output drive applied to a pad on the chip. The circuit includes a PVT monitor for providing an output that is related to process, voltage and temperature parameter variations on the chip. A processor determines network configuration information and enables the network's electrical or capacitance characteristics to be determined. The processor is responsive to an output from the PVT monitor and the network's determined electrical characteristics to provide control outputs indicative of a required output drive current level. A drive current circuit includes alterable circuitry and is responsive to the processor's control output to provide the required output drive levels to the pad.

REFERENCES:
patent: 4383216 (1983-05-01), Dorler et al.
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4623805 (1986-11-01), Flora et al.
patent: 4641048 (1987-02-01), Pollock
patent: 4684897 (1987-08-01), Richards et al.
patent: 4691124 (1987-09-01), Ledzius et al.
patent: 4815113 (1989-03-01), Ludwig et al.
patent: 4818901 (1989-04-01), Young et al.
patent: 4939389 (1990-07-01), Cox et al.
patent: 5086238 (1992-02-01), Watanabe et al.
patent: 5198758 (1993-03-01), Iknaian et al.
patent: 5198759 (1993-03-01), Ohnosorge
patent: 5272390 (1993-12-01), Watson, Jr. et al.
"Designers Seek Reduction of Electrical Noise", N. Kumar, ASiC Technology & News, Jul. 1990.
"VLSI Performance Compensation for Off-Chip Drivers and Clock Generation", D. Cox et al., IEEE 1989 Custom Integrated Circuits Conference.
"A 50-ns 16-Mb DRAM with a 10-ns Data Rate and On-Chip ECC", H. Kalter et al., IEEE Journal of Solid State Circuits, vol. 25, No. 5, Oct. 1990.
"A 300k-Circuit ASIC Logic Family", J. Petrovick, et al., 1990 IEEE International Solid-State Circuits Conference Feb. 15, 1990.
"Process-Independent Delay Driver", IBM Tech. Disclosure Bulletin, vol. 23, No. 9, Feb. 1981.
"Delay and Power Tolerance Regulator for FET Logic", K. King et al., IBM Tech. Discl. Bulletin, vol. 23, No. 4, Sep. 1980.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programmable integrated circuit output pad does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable integrated circuit output pad, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable integrated circuit output pad will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-221219

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.