Programmable integrated circuit logic array device having improv

Details Programmable integrated circuit logic array device having improv Programmable integrated circuit logic array device having improv

1987-03-02

1990-11-06

Shaw, Gareth D.

Boots, shoes, and leggings

36496577, 364949, 3649492, 3649278, 3649481, 364716, 307465, H03K 19177, G06F 738

Patent

active

049691210

ABSTRACT:
A programmable integrated circuit logic array device having one or more of the following features: (1) a bus port for receiving data directly from or making data available directly to an associated microprocessor or other similar device, (2) an internal bus (preferably with internal bus arbitration logic for resolving competing demands for utilization of the bus) for conveying data between the bus port and the logic arrays and/or between the logic arrays themselves, (3) the ability to operate either in an edge-trigger mode (in which controlled functions such as input registers are triggered by the transitional edges of control signals) or in a flow-through mode (in which controlled functions such as input registers are triggered by the states rather than the transitional edges of the control signals), and (4) the ability to operate either in a fast mode (in which timing control signals are applied substantially directly to the elements to be controlled) or in a slow mode (in which timing control signals propagate through the logic arrays rather than being applied directly to the elements to be controlled).

REFERENCES:
patent: 3912947 (1975-10-01), Buchanan
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4238833 (1980-12-01), Ghest et al.
patent: 4281380 (1981-07-01), DeMesa et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4742252 (1988-05-01), Agrawal
D. Bursky, "Design Bus Interfaces, Peripherals with Programmable-Logic Chip", Electronic Design, Aug. 20, 1987, pp. 50-52, 54.
D. Faria, "High Density EPLD's With Second Generation Architecture Features", 8079 Electro/86 and Mini/Micro Northeast 11 (1986) Conference Record, vol. 18, No. 2, pp. 1-14.
D. J. Brain, "EPROM Technology Enhances CMOS PAL Performance", New Electronics, vol. 18, No. 4, Feb. 19, 1985, pp. 72-73.
R. F. Hartmann, "CMOS Erasable Programmable Logic Devices TTL Replacement Made Easy", 8079 Electro and Mini/Micro Northeast, vol. 11, No. 1, Apr. 23-25, 1985, pp. 1-9.
J. C. Leininger, "Universal Logic Module", IBM Technical Disclosure Bulletin, vol. 13, No. 5, Oct. 1970, pp. 1294-1295.

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