Programmable instruction trap system and method

Details Programmable instruction trap system and method Programmable instruction trap system and method

1998-02-18

1999-04-20

Treat, William M.

395591, 39518311, 39518314, G06F 1100

Patent

active

058965262

ABSTRACT:
A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially. Related Applications

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J.T. Brady, Compare and Conditionally Interrupt, IBM Technical Disclosure Bulletin, vol. 20, No. 7, Dec. 1977.

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